
/*----------------------------------------------------------------------------
 * Copyright (c) <2013-2015>, <Huawei Technologies Co., Ltd>
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 * conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 * of conditions and the following disclaimer in the documentation and/or other materials
 * provided with the distribution.
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific prior written
 * permission.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
 * Notice of Export Control Law
 * ===============================================
 * Huawei LiteOS may be subject to applicable export control laws and regulations, which might
 * include those applicable to Huawei LiteOS of U.S. and the country in which you are located.
 * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such
 * applicable export control laws and regulations.
 *---------------------------------------------------------------------------*/
#include "stdio.h"
#include "stdlib.h"
#include "los_atomic.h"
#include "hisoc/usb3.h"
#include "asm/hal_platform_ints.h"
#include "asm/delay.h"

#define USB3_PHY   IO_ADDRESS(MISC_REG_BASE + 0x88)
#define PORT0_CTRL   IO_ADDRESS(MISC_REG_BASE + 0x38)
#define USB3_CTRL   IO_ADDRESS(CRG_REG_BASE + 0x190)
#define USB3_COMBPHY    IO_ADDRESS(CRG_REG_BASE + 0x188)
#define USB2_PHY    IO_ADDRESS(CRG_REG_BASE + 0x184)
#define USB3_VCC_SRST_REQ    (0x1U << 16)
#define U3_ENABLE   (0x1U << 3)
#define COMBPHY_SRST_REQ    (0x1U << 0)
#define USB2_PHY0_PORT_TREQ (0x1U << 3)
#define USB3_UTMI_CKSEL        (0x1U << 29)
#define USB2_PHY0_CKEN      (0x1U << 5)
#define USB2_PHY0_REQ       (0x1U << 1)
#define COMBPHY0_REF_CKEN   (0x1U << 8)
#define PCS_SSP_SOFT_RESET    (0x1U << 31)
#define PORT_CAP_DIR        (0x3 << 12)
#define DEFAULT_HOST_MOD    (0x1U << 12)
#define SUSPEND_USB3_SS_PHY    (0x1U << 17)
#define PERI_USB3_GTXTHRCFG    0x2310000
#define REG_GUSB3PIPECTL0   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE_FOR_PORT1 + 0xc2c0)
#define GTXTHRCFG   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE_FOR_PORT1 + 0xc108)
#define USB3_REG_GCTL    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE_FOR_PORT1 + 0xc110)

#define USB2_REG_GCTL    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE_FOR_PORT2 + 0xc110)
#define USB2_VCC_SRST_REQ    (0x1U << 0)
#define USB2_PHY1_PORT_TREQ (0x1U << 2)
#define USB2_UTMI_CKSEL        (0x1U << 13)
#define USB2_PHY1_CKEN      (0x1U << 4)
#define USB2_PHY1_REQ       (0x1U << 0)

static int otg_usbdev_stat = 0;

void hiusb3_host2device(void)
{
    unsigned int reg;
#if defined(LOSCFG_DRIVERS_USB3_HOST_FOR_PORT1) || defined(LOSCFG_DRIVERS_USB3_DEVICE_FOR_PORT1)
    reg = GET_UINT32(USB3_REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<13); /*[13:12] 01: Host; 10: Device; 11: OTG*/
    WRITE_UINT32(reg, USB3_REG_GCTL);
#else
    reg = GET_UINT32(USB2_REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<13); /*[13:12] 01: Host; 10: Device; 11: OTG*/
    WRITE_UINT32(reg, USB2_REG_GCTL);
#endif
    udelay(20);
}

static long dev_open_cnt = 0;

void hisi_usb3_crg_config(void)
{
    unsigned int reg;

    /*U3 vcc reset*/
    reg = GET_UINT32(USB3_CTRL);
    reg |= USB3_VCC_SRST_REQ;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(100);

    /*enable ss port*/
    reg = GET_UINT32(PORT0_CTRL);
    reg &= ~U3_ENABLE;
    WRITE_UINT32(reg, PORT0_CTRL);
    udelay(100);

    /*combphy reset*/
    reg = GET_UINT32(USB3_COMBPHY);
    reg &= ~COMBPHY_SRST_REQ;
    WRITE_UINT32(reg, USB3_COMBPHY);
    udelay(100);

    /*release TPOR default release*/
    reg = GET_UINT32(USB2_PHY);
    reg &= ~USB2_PHY0_PORT_TREQ;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*utmi clock sel*/
    reg = GET_UINT32(USB3_CTRL);
    reg &= ~USB3_UTMI_CKSEL;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(200);

    /*open phy ref clk default open*/
    reg = GET_UINT32(USB2_PHY);
    reg |= USB2_PHY0_CKEN;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*U2 phy reset release*/
    reg = GET_UINT32(USB2_PHY);
    reg &= ~USB2_PHY0_REQ;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*open ref CKEN*/
    reg = GET_UINT32(USB3_COMBPHY);
    reg |= COMBPHY0_REF_CKEN;
    WRITE_UINT32(reg, USB3_COMBPHY);
    udelay(100);

    /*U3 PHY reset release*/
    reg = GET_UINT32(USB3_COMBPHY);
    reg &= ~COMBPHY_SRST_REQ;
    WRITE_UINT32(reg, USB3_COMBPHY);
    udelay(100);

    /*config U3 Controller release*/
    reg = GET_UINT32(USB3_CTRL);
    reg &= ~USB3_VCC_SRST_REQ;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(100);
}

void hisi_usb3_ctrl_config(VOID)
{
    unsigned int reg;

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg |= PCS_SSP_SOFT_RESET;
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
    udelay(200);

    /* u3 port default host */
    reg = GET_UINT32(USB3_REG_GCTL);
    reg &= ~PORT_CAP_DIR;
    reg |= DEFAULT_HOST_MOD;
    WRITE_UINT32(reg, USB3_REG_GCTL);
    udelay(20);

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg &= ~PCS_SSP_SOFT_RESET;
    reg &= ~SUSPEND_USB3_SS_PHY;
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
    udelay(20);

    WRITE_UINT32(PERI_USB3_GTXTHRCFG, GTXTHRCFG);
    udelay(20);
}

void hisi_usb3_eye_config(void)
{

}

static int hisi_usb3_phy_power_off(void)
{
    unsigned int reg;
    if (LOS_AtomicDecRet((void *)&dev_open_cnt) == 0) {
    /*U3 vcc reset*/
    reg = GET_UINT32(USB3_CTRL);
    reg |= USB3_VCC_SRST_REQ;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(100);

    /*combphy reset*/
    reg = GET_UINT32(USB3_COMBPHY);
    reg &= ~COMBPHY_SRST_REQ;
    WRITE_UINT32(reg, USB3_COMBPHY);
    udelay(100);
    }
    return 0;
}

static int hisi_usb3_phy_power_on(void)
{
    if (LOS_AtomicIncRet((void *)&dev_open_cnt) == 1) {
        hisi_usb3_crg_config();
        hisi_usb3_ctrl_config();
        hisi_usb3_eye_config();
    }
    return 0;
}

void hisi_usb_crg_config(void)
{
    unsigned int reg;

    /*U2 vcc reset*/
    reg = GET_UINT32(USB3_CTRL);
    reg |= USB2_VCC_SRST_REQ;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(100);

    /*release TPOR default release*/
    reg = GET_UINT32(USB2_PHY);
    reg &= ~USB2_PHY1_PORT_TREQ;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*utmi clock sel*/
    reg = GET_UINT32(USB3_CTRL);
    reg &= ~USB2_UTMI_CKSEL;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(200);

    /*open phy ref clk default open*/
    reg = GET_UINT32(USB2_PHY);
    reg |= USB2_PHY1_CKEN;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*U2 phy reset release*/
    reg = GET_UINT32(USB2_PHY);
    reg &= ~USB2_PHY1_REQ;
    WRITE_UINT32(reg, USB2_PHY);
    udelay(200);

    /*config U2 Controller release*/
    reg = GET_UINT32(USB3_CTRL);
    reg &= ~USB2_VCC_SRST_REQ;
    WRITE_UINT32(reg, USB3_CTRL);
    udelay(100);
}

void hisi_usb_ctrl_config(void)
{
    unsigned int reg;

    /* u2 port default host */
    reg = GET_UINT32(USB2_REG_GCTL);
    reg &= ~PORT_CAP_DIR;
    reg |= DEFAULT_HOST_MOD;
    WRITE_UINT32(reg, USB2_REG_GCTL);
}

void hisi_usb_eye_config(void)
{

}

static int hisi_usb_phy_power_on(void) /*lint -e528*/
{
    if (LOS_AtomicIncRet((void *)&dev_open_cnt) == 1) {
        hisi_usb_crg_config();
        hisi_usb_ctrl_config();
        hisi_usb_eye_config();
    }
    return 0;
}

static int hisi_usb_phy_power_off(void) /*lint -e528*/
{
    unsigned int reg;

    if (LOS_AtomicDecRet((void *)&dev_open_cnt) == 0) {
        /*U2 vcc reset*/
        reg = GET_UINT32(USB3_CTRL);
        reg |= USB2_VCC_SRST_REQ;
        WRITE_UINT32(reg, USB3_CTRL);
        udelay(100);
    }
    return 0;
}

void hiusb3_start_hcd(void)
{
#if defined(LOSCFG_DRIVERS_USB3_HOST_FOR_PORT1) || defined(LOSCFG_DRIVERS_USB3_DEVICE_FOR_PORT1)
    (void)hisi_usb3_phy_power_on();
#else
    (void)hisi_usb_phy_power_on();
#endif
}
void hiusb3_stop_hcd(void)
{
#if defined(LOSCFG_DRIVERS_USB3_HOST_FOR_PORT1) || defined(LOSCFG_DRIVERS_USB3_DEVICE_FOR_PORT1)
    (void)hisi_usb3_phy_power_off();
#else
    (void)hisi_usb_phy_power_off();
#endif
}

int hiusb_is_device_mode(void)
{
    return (otg_usbdev_stat == 1);
}

void usb_otg_sw_set_device_state(void)
{
    otg_usbdev_stat = 1;
}

void usb_otg_sw_clear_device_state(void)
{
    otg_usbdev_stat = 0;
}

